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| mas 3506d worldspace broadcast channel edition july 25, 2001 6 251-433-1pd preliminar y d a t a sheet micr onas micronas audio decoder
mas 3506d preliminary data sheet 2 micronas contents page section title 4 1. introduction 4 1.1. features of the mas 3506d 4 1.2. system overview 7 2. functional description of the mas 3506d 72.1.overview 7 2.2. firmware (internal program rom) 7 2.2.1. broadcast channel synchronization 8 2.2.1.1. broadcast channel timing 8 2.2.1.2. buffer-controlled loop 8 2.2.2. broadcast channel demultiplexing 8 2.2.3. mpeg audio decoding 8 2.2.4. baseband processing 9 2.3. clock management 9 2.4. power supply concept 9 2.4.1. internal voltage monitor 9 2.4.2. dc/dc converter 9 2.4.3. stand-by functions 9 2.4.4. start-up sequence 10 2.5. interfaces 10 2.5.1. broadcast channel (bc) input interface 11 2.5.2. parallel input output interface (pio) 12 2.5.3. audio output interface 13 3. controlling 13 3.1. i 2 c-access 13 3.1.1. device address 13 3.1.2. i 2 c registers and subaddresses 13 3.1.3. conventions for the command description 14 3.2. i 2 c control register (subaddress 6a hex ) 15 3.3. i 2 c-data register (subaddresses 68 hex and 69 hex ) and the mas 3506d dsp-command syntax 16 3.3.1. data formats 16 3.3.2. run and freeze (codes 0 hex to 1 hex ) 16 3.3.3. select service component (code 5 hex ) 16 3.3.4. read ancillary mpeg data (code 6 hex ) 18 3.3.5. read sch-data (code 8 hex ) 18 3.3.6. write register (code 9 hex ) 19 3.3.7. write memory (codes a hex and b hex ) 19 3.3.8. read register (code d hex ) 19 3.3.9. read memory (codes e hex and f hex ) 19 3.3.10. default read 20 3.4. control registers 23 3.5. control and status memory 28 3.5.1. volume matrix contents, continued page section title preliminary data sheet mas 3506d micronas 3 30 4. specifications 30 4.1. outline dimensions 31 4.2. pin connections and short descriptions 33 4.3. pin descriptions 33 4.3.1. power supply pins 33 4.3.2. dc/dc converter pins 33 4.3.3. control lines 33 4.3.4. parallel interface control lines 33 4.3.5. parallel interface data lines 34 4.3.6. voltage supervision and other functions 34 4.3.7. serial input interface 35 4.3.8. serial output interface 35 4.3.9. miscellaneous 35 4.4. pin configuration 36 4.5. internal pin circuits 37 4.6. electrical characteristics 37 4.6.1. absolute maximum ratings 37 4.6.2. recommended operating conditions 39 4.6.3. characteristics 40 4.6.3.1. i 2 c characteristics 41 4.6.3.2. timing of pio-signals 42 4.6.3.3. i 2 s bus characteristics ? sdi 43 4.6.3.4. i 2 s characteristics ? sdo 43 4.6.3.5. firmware characteristics 44 4.6.4. dc/dc converter characteristics 46 4.6.5. typical performance characteristics 52 5. data sheet history mas 3506d preliminary data sheet 4 micronas worldspace broadcast channel audio decoder 1. introduction the worldspace system is a satellite-based digital radio service for direct-to-home transmission of digital radio programs. the coverage areas of this service are africa, south america, and parts of asia. the mas 3506d is the source decoder of micronas ? starman chip set that is designed for the reception of worldspace signals. the mas 3506d extracts one service component (sc) of an incoming digital world- space broadcast channel (bc) and decodes mpeg 1/2/2.5 layer 3 1) encoded audio data con- tained in the selected service component. the ser- vice control header (sch) information from the broadcast channel is accessible via the embedded fast mode serial control interface. the mas 3506d provides digital audio data output in i 2 s and similar for- mats. an embedded digital buffer-controlled loop recovers the sampling frequency of the audio signal and generates a synchronized 24.576 mhz clock sig- nal which is used as an oversampling clock for d/a converters. a block diagram of the mas 3506d is shown in figure 1 ? 2 on page 5. 1) mpeg 2.5 is a compatible extension of mpeg 2 audio, defined in iso/iec 13818-3.2 that covers additionally very low sampling frequencies down to 8khz. 1.1. features of the mas 3506d ? single-chip worldspace broadcast channel bit- stream demultiplexer ? iso mpeg 1/2/2.5 layer 3 decoder ? iso mpeg compliance tests passed ? data processing by a high-performance risc dsp core (masc) ? download feature provides additional functionality ? self-synchronized operation ? output audio data delivered (in various formats) via an i 2 s bus (sdo) ? digital volume control and stereo channel mixer ? automatic soft-mute function ? worldspace sch-data output via i 2 c interface ? mpeg ancillary data provided via i 2 c interface ? status information accessible via pio pins or i 2 c ?? crc error ? , ? mpeg frame synchronization ? and ? bc-frame-synchronization ? indicators ? power management for reduced power consump- tion at lower sampling frequencies ? low power dissipation (30 mw at fs 12 khz, 46 mw at fs 24 khz, 86 mw at fs > 24 khz at 2.7 v) ? supply voltage range: 2.7 v to 3.6 v ? adjustable built-in dc/dc up-converter for one-cell and two-cell battery operation (typically down to v bat =0.9v) ? adjustable power supply supervision ? power-off function 1.2. system overview the micronas starman chip set consists of the channel decoder drd 3515a and the mpeg layer 3 audio decoder mas 3506d. all essential analog and digital building blocks for worldspace reception are provided by the chip set. together with an l-band tuner and an appropriate microcontroller this set creates a complete starman radio receiver (figure 1 ? 1) fig. 1?1: standard application of the starman chip set since the drd 3515a also contains an audio amplifier for headphone or small loudspeaker operation, only a minimum of external components is necessary. the additional inputs for analog signals (e.g. conventional am/fm receiver, tape etc.) make the amplifier accessi- ble to these audio sources and thus considerably sim- plify the design of complete radio receivers. the analog audio output of the worldspace signal can be connected to an external stereo amplifier for higher power or quality. also a digital audio signal in standard i 2 s format is provided for high-end applications that may require an external d/a converter. am/fm receiver, tape player worldspace tuner system controller drd 3515a mas 3506d aux1/2 (analog) if input bc i 2 s sc-out analog out i 2 c preliminary data sheet mas 3506d micronas 5 the complete worldspace broadcast channel (bc) is available as a serial output signal from the drd 3515a and provides full access to all worldspace data. the additional service component (sc) output of the drd 3515a may be useful in applications where a data and an audio channel are transmitted simulta- neously. in this case, the data component is directed to the sc output. this function is independent from the audio service component extraction in the mas 3506d. service control header data are available via i 2 c con- troller interface from the mas 3506d. (n.b. the time slot control channel data are available only from the drd 3515a.) fig. 1 ? 2: block diagram of the mas 3506d clock synthe- sizer serial input interface serial output interface rclk oclk 14.725 mhz 24.576 mhz bc in audio data out to drd 3515a service component extraction from broadcast channel mpeg 1/2/2.5 layer 3 audio decoding buffer-controlled loop 20-bit risc dsp i 2 c interface parallel interface dc/dc converter vdd to c mas 3506d preliminary data sheet 6 micronas fig. 1 ? 3: complete worldspace receiver block diagram audio out fm/am demod. drd3515a MAS3506D c left right lcd mono a line stereo keys 3.0 v 3 pup wrdy pup clki fm/am antenna double superhet l-band tuner pol.- switch satellite antenna bcdout bcc scdout scc to optional bc processing to optional sc processing scw bcdin bcenable bc data input from ext. processing regulated voltage (3 v) sci-control bus dcen wsen dc/dc con- verter mpeg layer 3 decoder buffer- controlled clock synthesizer qpsk dem. and timing recovery fec and tdm demux d/a and analog audio 4 oclk 24.576 mhz digital audio input buffer sc extr. output buffer 14.725 mhz 1 rclk 2nd if 2 cb preliminary data sheet mas 3506d micronas 7 2. functional description of the mas 3506d 2.1. overview the hardware of the mas 3506d consists of a high- performance risc digital signal processor (dsp) and appropriate interfaces for worldspace broadcast channel decoding (see figure 2 ? 1). the internal pro- cessor works with a memory word length of 20 bits and an extended range of 32 bits in its accumulators. the instruction set of the dsp is highly optimized for audio data compression and decompression. thus, only very small areas of internal ram and rom are required. all the data input and output actions are based on a ? non- cycle-stealing ? background dma that does not cause any computational overhead (except for some initial- ization). the overall function of the mas 3506d can be altered by downloading up to 1 kword of program code into the internal ram and executing this code instead of the built-in firmware rom code 1) . dedicated clock management hardware supports synchronization on the transmitted data signal. a dc/dc step-up con- verter has been integrated for efficient battery-based operation. fig. 2 ? 1 shows the building blocks of the mas 3506d. 1) detailed information about downloading is provided in combination with the mas 3506d software devel- opment package or together with the mas 3506d software modules available from micronas. 2.2. firmware (internal program rom) the firmware of the mas 3506d operates on the broadcast channel signal generated by the drd 3515a. the mas 3506d firmware processes the input signal in four steps. ? broadcast channel synchronization ? broadcast channel demultiplexing ? mpeg audio decoding ? frame synchronization and decoding error signals are provided at output pins of the mas 3506d. 2.2.1. broadcast channel synchronization the mas 3506d analyzes the incoming bc bitstream and detects the service control header (sch) pream- ble. if the preamble is found, the bc-sync signal (available at a mas 3506d output pin) indicates that the mas 3506d is in synchronized state. if synchroni- zation is lost, the mas 3506d automatically resets the bc-sync signal and performs an audio soft-mute until the next sc-header is detected. fig. 2 ? 1: functional overview of the mas 3506d oclk bc input digital audio output clock synthesizer volume matrix sch buffer configuration registers sch synchro- service component selection layer 3 status data buffer ancillary data mpeg 1/2/2.5 layer 3 decoder nization to c (i 2 c) to drd 3515a mas 3506d preliminary data sheet 8 micronas 2.2.1.1. broadcast channel timing the incoming broadcast channel bitstream has a framing with a period between prime rate channel preambles (prcp) of prcpt = 432 ms during one frame the transmission of the bc is inter- rupted by a gap prcpgap of: prcpgap = 2.5 ms the data transmission is interrupted by a second gap mfpgap with a duration of mfpgap = 1.2 ms that is synchronous with the master frame preamble (mfp) cycle with a period of: mfpt = 138 ms both cycles mfpt and prcpt have a least common multi- ple at 9936 ms. these gaps are independent of the number of prime rate channels (prc) n that create the considered broadcast channel. 2.2.1.2. buffer-controlled loop for the recovery of the audio sample clock, a buffer- controlled loop is used that operates on the incoming broadcast channel bit stream. the buffer control loop characteristic suppresses the effects of these gaps on the stability of the generated audio sample frequency by more than 40 db. thus, no audible jitter is intro- duced to the derived reference clock for the d/a con- verter (see section 2.3. "clock management"). the step response of the buffer-controlled loop is plot- ted in figure 2 ? 2 with respect to different number of prcs. the settling time for the buffer-controlled loop is about 10 s. fig. 2 ? 2: buffer-controlled loop step response 2.2.2. broadcast channel demultiplexing the service control header that directly follows the sch-preamble in the bc bitstream is made accessible to the controller after it has been detected. its availabil- ity is indicated by the bc-frame-sync signal. infor- mation about the content of the broadcast channel is given in the service control header data. the control- ler may select the number of the service component that is to be passed to the internal mpeg audio decoder. by default, always service component ? 0 ? is decoded by the mas 3506d. an implemented autoscan mode can be selected that skips non-audio service components. 2.2.3. mpeg audio decoding the mpeg 1/2/2.5 layer 3 decoder performs the audio decoding. the steps for decoding are: ? synchronization ? side information extraction ? huffman decoding ? synthesis filter bank ? ancillary data extraction the bit rates and sampling rates that are supported by the mas 3506d are listed in table 2 ? 1. frame synchronization and decoding error signals are provided at output pins of the mas 3506d. 2.2.4. baseband processing a digital volume control matrix is applied to the digital stereo audio data. this matrix may also perform addi- tional balance control and a simple kind of stereo basewidth enhancement. the four factors ll, lr, rl, and, rr are adjustable via the controller with 20 bit resolution (see fig. 3 ? 2 on page 28). 4.3 8.6 13 17 21 0.02 0.04 0.06 0.08 0.1 0.12 t/s table 2 ? 1: sampling frequencies and bit rates sampling freq. in khz bit rates in kbit/s 48, 32, 24, 16, 12, 8 128, 112, 96, 80, 64, 56, 48, 40, 32, 24, 16, 8 preliminary data sheet mas 3506d micronas 9 2.3. clock management the complete starman chip set is driven by a single crystal with a nominal frequency of 14.725 mhz. the drd 3515a contains the crystal oscillator and an appropriate clock buffer to generate the clock signal rclk . this rclk signal is used as reference clock for the mas 3506d by an internal clock synthesizer that generates an internal system clock of 24.576 mhz. this synchronized clock frequency is passed back to the drd 3515a for use in its embedded audio d/a converter. 2.4. power supply concept the mas 3506d offers an embedded controlled dc/ dc converter for battery based power supply con- cepts. it works as an up-converter. 2.4.1. internal voltage monitor an internal voltage monitor compares the input voltage at the vsens pin with an internal reference value that is adjustable via i 2 c bus. the pup output pin should be observed by the controller. it becomes inactive when the voltage at the vsens pin drops below the programmed value of the reference voltage. it is important that the wsen must not be activated before the pup signal is generated. the pup signal thresholds are listed in table 3 ? 10 on page 20. the internal voltage monitor will be activated with a high level at pin dcen. 2.4.2. dc/dc converter the dc/dc converter of the mas 3506d is used to generate a fixed power supply voltage even if the chip set is powered by battery cells in portable applications. the dc/dc converter is designed for the application of 1 or 2 batteries or nicd cells as shown in fig. 2 ? 5 which shows the standard application circuit. the dc/ dc converter is switched on by activating the dcen pin. its output power is sufficient for supplying the com- plete radio receiver. note : connecting dcen directly to vdd leads to unexpected states of the dccf register. a 22 h inductor is required for the application. the important specification item is the inductor saturation current rating, which should be greater than 2.5 times the dc load current. the dc resistance of the inductor is important for efficiency. the primary criterion for selecting the output filter capacitor is low equivalent series resistance (esr), as the product of the inductor current variation and the esr determines the high-fre- quency amplitude seen on the output voltage. the schottky diode should have a low voltage drop v d for a high overall efficiency of the dc/dc converter. the current rating of the diode should also be greater than 2.5 times the dc output current. the vsens pin has to be always connected to the output voltage. 2.4.3. stand-by functions a high level at pin wsen enables both, the dsp including the i 2 c-block and the dc/dc-converter. if the dsp-functions (audio decoding) are not needed, the dc/dc-converter may remain active to supply other parts of the radio. this mode is entered by set- ting dcen to ? high ? and wsen to ? low ? . no i 2 c control is possible in this mode. 2.4.4. start-up sequence the dc/dc converter starts from a minimum input voltage of 0.9 v. there should be no output load dur- ing startup. wsen must be ? low ? . the start-up script should be as follows: 1. start the dc/dc-converter with a high signal (vdd, avdd) at pin dcen. 2. wait until pup goes ? high ? . 3. it is recommended to wait at least one millisecond to guarantee that the output voltage has settled. 4. the controller may now enable the dsp with a ? high ? signal at pin ? wsen ? . please also refer to figure 2 ? 3. fig. 2 ? 3: dc/dc operation >0.9v wsen > 2 v dcen 1 dsp operation controller dc/dc on button mas 3506d preliminary data sheet 10 micronas 2.5. interfaces the mas 3506d uses an i 2 c control interface, a serial input interface for the broadcast channel, and a digital audio output interface for the decoded audio data (i 2 s or similar). additionally, a general-purpose parallel i/o interface (pio) may be used for monitoring and mode- selection tasks. the pio lines are controlled by the internal firmware. 2.5.1. broadcast channel (bc) input interface the bc input interface consists of the three pins sic, sii, and sid. for worldspace operation the sii pin is always to be connected to vss. the broadcast chan- nel input signal format is shown in figure 2 ? 4. the data values are latched with the falling edge of the sic signal. the input interface is asynchronous and accepts data streams generated by the drd 3515a bc output. fig. 2 ? 4: schematic timing of the sdi (bc) input the bc input can be switched to an alternate port. this function is controlled by input pin pi18. for more details please see section 3.1.3. on page 13 l fig. 2 ? 5: dc/dc converter connections 76543210 t siclk l t bw bcc (sic) bcd (sid) v h v i v h v i 0...15 32...47 64...94 10 16 ? + ? + vss avss avdd vdd clki dcso dcsg dcen pup wsen vsense 9 47 k ? 47 k ? power-on push button 10 k ? 10 nf dc/dc converter voltage monitor start-up oscillator controller 22 h v in 0.9 v c out 330 f low esr c in 330 f dccf 8e hex optional filter start-up oscillator +32 x2 preliminary data sheet mas 3506d micronas 11 2.5.2. parallel input output interface (pio) the parallel interface of the mas 3506d consists of the lines pi0..pi4, pi8, pi12..pi19: these signals are used to indicate the status of the broadcast channel and the mpeg layer 3 decoder. the pio pin status is also accessible via i 2 c interface (see table 3 ? 10). table 2 ? 2: pio input and output pin assignment during mpeg decoding pio pin name comment pi19 (o) bc-frame-toggle 0 1 output level tog- gled each bc- frame pi18 (i) bcinenable 0 1 enables si* inputs enables si inputs pi13 (o) bc-frame-sync 0 1 start of new frame p12 (o) bc-sync 0 1 unsynched synched to bc pi8 (o) mpeg-crc-error 0 1 no error crc-error or sync lost pi4 (o) mpeg-frame-sync 0 1 sync to a new mpeg frame pi3 (i) aud-sw may be used to monitor a signal indicating switch- ing between headphone and loudspeaker mode. pi2, pi1, pi0 (i) reserved the pi-pins may be monitored by reading the pio register (see table 3 ? 10) mas 3506d preliminary data sheet 12 micronas 2.5.3. audio output interface the audio output interface of the mas 3506d is a standard serial audio interface. the interface is config- urable by software to work in 16-bit/sample and 32-bit/ sample mode. the default setup is a 16-bit mode which is also the default setting for the drd 3515a. the 32-bit/sample mode is provided for high-resolution d/a converters that expect more than 16-bit/sample input data. the embedded d/a-converter of the drd 3515a is also capable of decoding the 32-bit/ sample format and provides a slightly better s/n per- formance in this mode 1) . the audio output interface timing is shown in figure 2 ? 6 and figure 2 ? 7. 1) if the 32-bit mode is selected and the d/a converter of the drd 3515a is still connected, it also has to be switched to 32-bit i 2 s mode. fig. 2 ? 6: schematic timing of the digital audio output interface in 16-bit/sample mode fig. 2 ? 7: schematic timing of the digital audio output interface in 32-bit/sample mode dad v h v l 15141312111098 76543210 15141312111098 76543210 left 16-bit audio sample right 16-bit audio sample 0 timing detail v h v l dai 15 dai dad dad v h v l left 32-bit audio sample right 32-bit audio sample 0 timing detail v h v l dai 131 0 31 0 31 preliminary data sheet mas 3506d micronas 13 3. controlling 3.1. i 2 c-access communication between the mas 3506d and the external controller is done via an i 2 c slave interface. 3.1.1. device address the device addresses are 3a hex for writing (dw) and 3b hex for reading (dr), respectively. i 2 c clock syn- chronization is used to slow down the bus if required. 3.1.2. i 2 c registers and subaddresses the interface uses one level of subaddresses. the mas 3506d interface has 3 subaddresses allocated for the corresponding i 2 c-registers. the address 6a hex is used for basic control, i.e. reset and task select. the other addresses are used for data transfer from/to the mas 3506d. the i 2 c-control and data registers of the mas 3506d are 16 bits wide, the msb is denoted as bit [15]. trans- missions via i 2 c-bus have to take place in 16-bit words (two byte transfers, msb sent first); thus for each reg- ister access two 8-bit data words must be sent/ received via i 2 c-bus. 3.1.3. conventions for the command description the description of the various controller commands uses the following formalism: ? abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don ? t care ? memory addresses like d1:89f are always in hexa- decimal notation. ? a data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble. ? data values in nibbles are always shown in hexa- decimal notation. ? a hexadecimal 20-bit number d is written, e.g. as d = 17c63 hex , its five nibbles are d0 = 3 hex , d1 = 6 hex , d2 = c hex , d3 = 7 hex , and d4 = 1 hex . ? variables used in the following descriptions: dw 3a hex i 2 c-device write dr 3b hex i 2 c-device read data_write 68 hex data register write data_read 69 hex data register read control 6a hex control register write ? bus signals sstart pstop a ack = acknowledge n nak = not acknowledge w wait = a wait time ( 4 ms) may occur ? symbols in the telegram examples < start condition > stop dd data byte xx ignore all telegram digits are hexadecimal, data originating from the mas 3506d are grayed. example: <3a 68 dd dd > write data to dsp <3a 69 <3b dd dd > read data from dsp figure 3 ? 1 shows i 2 c bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the i 2 c-device address with the read command (dr). fields with sig- nals/data originating from the mas 3506d are marked by a gray background. note that in some cases the data reading process must be concluded by a nak condition. the mas 3506d firmware scans the i 2 c interface peri- odically and checks for pending or new commands. table 3 ? 1: i 2 c device address bits a6 a5 a4 a3 a2 a1 a0 write/ read 00111010/1 table 3 ? 2: i 2 c subaddresses sub- address i 2 c- register function 68 hex data_write controller writes to mas 3506d data register 69 hex data_read controller reads from mas 3506d data register 6a hex control controller writes to mas 3506d control register mas 3506d preliminary data sheet 14 micronas the commands are then executed by the dsp during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. however, due to some time critical firmware parts, a certain latency time for the response has to be expected at the locations marked with a ? w ? (= wait). the theoretical worst case response time does not exceed 4 ms. however, the typical response time is less than 0.5 ms. 3.2. i 2 c control register (subaddress 6a hex ) the i 2 c control register is a write-only register. its main purpose is the software reset of the mas 3506d. the software reset is done by writing a 16-bit word to the mas 3506d with bit 8 set. the 4 least significant bits are reserved for task selection. the task selection is only useful in combination with download software. in the standard application these bits must always be set to 0. fig. 3 ? 1: i 2 c-bus protocol for the mas 3506d. signals originating from the mas 3506d are grayed. table 3 ? 3: control register data bit assignment 1) 1) x = don ? t care, r = reset, t3...t0 = task selection 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 xxxxxxxr0000t3t2t1t0 sdw control wa a a wa p d3,d2 d1,d0 w high byte data low byte data a p example: i 2 c write access sda scl 1 0 s p dr (3b hex ) example: i 2 c read access dw (3a hex ) data_read (69 hex ) sdw(3a hex )a data_write (68 hex ) a high byte data a low byte data a p n w = wait a = acknowledge (ack) n = not acknowledge (nak) s = start p = stop a s s a a a w w w w preliminary data sheet mas 3506d micronas 15 3.3. i 2 c-data register (subaddresses 68 hex and 69 hex ) and the mas 3506d dsp-command syntax the i 2 c data register is used to communicate with the internal firmware of the mas 3506d. it is readable (subaddress ? data_read ? ) and writable (subaddress ? data_write ? ) and also has a length of 16 bits. the data transfer is done with the most significant bit (m) first. a special command language is used that allows the controller to access the dsp-registers and ram-cells and thus monitor internal states, set the parameters for the dsp-firmware, control the hardware, and even pro- vide a download of alternative software modules. the dsp-commands consist of a ? code ? which is sent to to i 2 c-data register together with additional parameters. ta b le 3 ? 5 gives an overview over the different com- mands which the dsp-core may receive. the ? code ? is always the first data nibble transmitted after the ? data_write ? byte. the control interface is also used for low-bit-rate data transmission, i.e. mpeg-embedded ancillary data and the worldspace service control header. these data are available in a specified memory area of the mas 3506d after successful decoding. the synchroni- zation between controller and the mas 3506d will be done by observing the bc-frame-sync and mpeg- frame-sync signals in register c8 hex or at the corre- sponding pins. table 3 ? 4: data register bit assignment 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ml ... sdw data_write wa a a a code ,... ...,... table 3 ? 5: basic controller command codes for the mas 3506d code (hex) command function 0 run start execution of an internal program. run with start address 0 hex means freeze the operating system 1 run config start execution of an internal program and switch config ram to p-ram 5 select sc select the service component 6 read ancillary data read mpeg ancillary data 8 read sch-data read service control header 9 write register an internal register of the mas 3506d can directly be written to by the con- troller a, b write memory a block of the dsp memory can be written to by the controller. (this feature may be used to download alternate programs.) d read register the controller can read an internal register of the mas 3506d e, f read memory a block of the dsp memory can be read by the controller mas 3506d preliminary data sheet 16 micronas 3.3.1. data formats the internal data word size is 20 bits. all ram- addresses can be accessed in a 20-bit mode via i 2 c- bus. because of the 16-bit width of the i 2 c-data regis- ter the full transfer of all 20 bits requires two 16-bit i 2 c- words. some commands only access the lower 16 bits of a cell. for fast access of internal dsp-states the processor core also has an address space of 256 data registers. the internal data format is a 20 bit two ? s complement denoted ? r ? . if in some cases a fixed point notation ? v ? is necessary. the conversion between the two forms of notation is done as follows: r = v*524288.0+0.5; ( ? 1.0 v < 1.0) v = r/524288.0; ( ? 524288 < r < 524287) 3.3.2. run and freeze (codes 0 hex to 1 hex ) the run command causes the start of a program part at address a = (a3,a2,a1,a0). note that nibble a3 is also the command code (see table 3 ? 5) and thus it is restricted to certain values. this command is espe- cially used to start alternate code or downloaded code from a ram-area that has been configured as program ram. example 1: start program execution at address 345 hex : <3a 68 03 45> freeze is a special run command with start address 0. it suspends all normal program execution. the operat- ing system will enter an idle loop so that all registers and memory cells can be watched. this state is useful for operations like downloading code or contents of memory cells because the internal program cannot overwrite these values. this freezing will be required if alternative software is downloaded into the internal ram of the mas 3506d. freeze has the following i 2 c protocol: <3a 68 00 00> the entry point of the default software will be accessed automatically after a reset, thus issuing a run or freeze command is only necessary for starting down- loaded software or special program modules which are not part of the standard set. 3.3.3. select service component (code 5 hex ) select the (zero-based) service component with the number d = d0. the number of available service com- ponents is to be taken from the sch information. a maximum of 8 service components are allowed in one broadcast channel. sc-selection is also possible by writing to memory cell d1:7ef (see table 3 ? 11 on page 23). 3.3.4. read ancillary mpeg data (code 6 hex ) the availability of new ancillary data is indicated by the mpeg-frame-sync signal in register c8 hex or at the corresponding pin. ancillary data are available every 24 to 32 ms depending on the sample rate of the mpeg-bitstream. the instruction parameters are embedded in the 3 nibbles o2..o0. the 6 msbs indi- cate the address offset counted in 16-bit words where the read-out of the ancillary data shall start. the 6 lsbs indicate the number of 16-bit words that are to be transmitted by mas 3506d. sdw data_write waaawap a3,a2 a1,a0 table 3 ? 6: arrangement of o-bits 11 10 9 8 7 6 5 4 3 2 1 0 o2 o1 o0 address offset number of 16-bit words sdw data_write wa a a wa 5 ,0 0,0 p awa 0,0 0,d0 1) send command (read d0) 2) get ancillary data values sdw data_write wa a a wa 6 ,o2 o1,o0 sdw data_read wa a s a dr p p wa d3,d2 a d1,d0 n w d3,d2 a d1,d0 ....repeat for n data values.... w preliminary data sheet mas 3506d micronas 17 the data values that are returned are organized in the following table: the ancillary data values are copied in the reverse order into this data field where the last bit received is place at bit 0 of the data word at offset 3. the number of data words with content can be calculated as fol- lows: int [(numberofancillarybits-1)/16] + 1 limitations: ? the maximum number of data words that can be read out are 28. ? the upper limit for ancillary data bitrate is 9600 bps. ? the ancillary data are only valid for 6 ms after the mpeg-frame-sync signal. memory example: the mpeg bitstream contains 20 bits of ancillary data with the content f0f08 hex . then the ancillary data field content will be: telegram example: first get the content of ? number of ancillary bits ? : <3a device write ( i 2 c-address) 68 data write 60 81> code 6 hex , offset 2, count 1: get number of ancillary bits <3a 69 <3b initiate reading dd dd > and read number of bits calculate number of words to be read from the number of bits received (e.g. 20 bits require two words). <3a device write (i 2 c-address) 68 data write 60 c2> code 6 hex , offset 3, count 2: read two words from offset 3. <3a 69 <3b initiate reading dd dd and read two words dd dd > table 3 ? 7: content of ancillary data field offset content 0 bit 17..32 of mpeg header 1) 1) see address d1:7f6 in table 3 ? 11 on page 23 1 bit 12..16 of mpeg header 2) 2) see address d1:7f5 in table 3 ? 11 on page 23 2 number of ancillary data bits 3 last 16 bits of ancillary data ... 28 first 16 bits of ancillary data table 3 ? 8: ancillary data example offset content 0 bit 17..32 of mpeg header 1 bit 12..16 of mpeg header 214 hex (number of anc bits) 30f08 hex (bit-order reversed) 4xxxf hex mas 3506d preliminary data sheet 18 micronas 3.3.5. read sch-data (code 8 hex ) the availability of service control header data is indi- cated by the related status registers or the bc- frame-sync. the instruction parameters are embedded in the 3 nibbles o2..o0. the 6 msbs indi- cate half of the address offset counted in 16-bit words where the read out of the sch data shall start. the 6 lsbs indicate half of the number of 16-bit words that are to be transmitted by the mas 3506d. example: if 4 words starting with sch-word 10 shall be read out the command parameters o2..o0 have to be set to: thus the command sequence that is to be sent to the mas 3506d is: <3a device write (mas 3506d i 2 c-address) 68 data write 81 42> code 8 hex , 4 words from offset word 10 the data read sequence is then initialized by <3a dw (mas 3506d write address) 69 data read <3b dr (mas 3506d read address) then the mas 3506d will send the sch-values dd dd sch10.h, sch10.l dd dd sch11.h, sch11.l dd dd sch12.h, sch12.l dd dd > sch13.h, sch13.l where schx.h/l refers to the high/low part of the xth word of the sch. common parameters with command-code 8 hex often the four nibbles defining start address and amount to be transmitted (8 hex , o2, o1, o0) may have the following values: ? 80 04 : read 16 bytes (= 8 words, 6 lsbs = 4) from the beginning (offset = 0, 6 msbs = 0) of the sch (i.e. everything from the beginning up to adf2) ? 81 01 : read 4 bytes (= 2 words, 6 lsbs = 1) start- ing at 16 bytes (= 8 words, 6 msbs = 4) offset (i.e. one service component control field sccf) ? 81 05 : read 20 bytes (= 10 words, 6 lsbs = 5) starting at 16 bytes (= 8 words, 6 msbs = 4) offset (i.e. 5 service component control fields sccf) 3.3.6. write register (code 9 hex ) the controller writes the 20-bit value ( d = d4,d3,d2,d1,d0) into the mas 3506d register ( r = r1,r0). a list of registers needed for control pur- poses is given in table 3 ? 10 on page 20. example: writing the value 81234 hex into the register with the number aa hex : <3a 68 9a a8 12 34> table 3 ? 9: sch-command example 11 10 9 8 7 6 5 4 3 2 1 0 o2 o1 o0 000101000010 52 5 means offset of (10 16-bit-words)/2 2 means amount of (4 16-bit-words)/2 1) send command (read d0) 2) get sch-values sdw data_write waaawa 8 ,o2 o1,o0 sdw data_read wa a s a dr p p wa d3,d2 a d1,d0 n w d3,d2 a d1,d0 ....repeat for n data values.... w sdw data_write wa a a wa 9 ,r1 r0,d4 awap d3,d2 d1,d0 preliminary data sheet mas 3506d micronas 19 3.3.7. write memory (codes a hex and b hex ) the memory areas d0 and d1 can be written by using the codes a hex and b hex , respectively. with the write d0/d1 memory command n 20-bit memory cells in d0 can be initialized with new data. example: write 80234 hex to d1:456 has the following i 2 c protocol: <3a 68 b0 00 write d1 memory 00 01 1 word to write 04 56 start address 00 08 value = 80234 hex 02 34> 3.3.8. read register (code d hex ) the mas 3506d has an address space of 256 dsp- registers. some of the registers ( r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others control the internal program flow. in table 3 ? 10, the registers of interest are described in detail. in contrast to memory cells, registers cannot be accessed as a block but must always be addressed individually. example: read the content of the register c8 hex : <3a 68 dc 80> define register <3a 69 <3b xx xd dd dd > and read 3.3.9. read memory (codes e hex and f hex ) the mas 3506d has 2 memory areas called d0 and d1 using the codes e hex and f hex for their read com- mands, respectively. the read d0/d1 memory command gives the control- ler access to all 20 bits of the memory cells of the mas 3506d. the telegram for reading 3 words starting at location d1:100 is <3a 68 f0 00 00 03 01 00> <3a 69 <3b xx xd dd dd xx xd dd dd xx xd dd dd > 3.3.10.default read the default read command immediately returns the lower 16 bits of the main status cell ( ? status ? ) of the mas 3506d and may be used to poll the processor status. the meaning of the returned bits is given in the description of control memory cell d1:7ee in table 3 ? 11 on page 23. sdw data_write wa a a wa a ,0 0,0 wa x,x a x,d4 p awa n3,n2 n1,n0 awa a3,a2 a1,a0 wa d3,d2 a d1,d0 wa x,x a x,d4 wa d3,d2 a d1,d0 ....repeat for n data values.... 1) send command 2) get register value sdw data_write wa a a wa p d ,r1 r0,0 sdw data_read wa a wn d3,d2 s a dr a d1,d0 p wa x,x a x,d4 w 1) send command (read d0) 2) get register value sdw data_write wa a a wa e ,0 0,0 sdw data_read wa a wa x,x s a dr a x,d4 p awa n3,n2 n1,n0 awap a3,a2 a1,a0 wa d3,d2 a d1,d0 wa n x,x a x,d4 w d3,d2 a d1,d0 ....repeat for n data values.... w w sdw data_read wa a n s a dr p w d3,d2 a d1,d0 w mas 3506d preliminary data sheet 20 micronas 3.4. control registers the registers displayed in the following table can be read and written via i 2 c commands described (see section 3.3.6. and section 3.3.8.). note! registers not given in the tables must not be written. table 3 ? 10: control registers address (hex) r/w function default (hex) name 8e w dc/dc-converter frequency and voltage the i 2 c protocol is working only if the processor is active (wsen = 1). however, the setting for the dccf register will remain active if the wsen line is deasserted. 08000 dccf dc/dc-converter frequency the frequency is controlled with bits 13...10 and 8. setting bit [13:10] frequency/khz bit [8] = 0 frequency/khz bit [8] = 1 11 11 11 10 11 01 11 00 10 11 10 10 10 01 10 00 01 11 01 10 01 01 01 00 00 11 00 10 00 01 00 00 156 160 163 167 171 175 179 184 188 194 199 204 210 216 223 230 128 245 253 263 272 283 295 307 320 335 351 368 387 409 433 460 the divider for the clki input is determined by the content of the dccf register. this register allows 32 settings of the dc/dc con- verter clock frequency f dc : (eq 1) in order to reduce interference noise in am-reception, the oscillator frequency may be adjusted in 16 steps in order to allow the system controller to select a base frequency that does not interfere with an other application. the following algorithm may be used to select an appropriate value for dccf: f sw f ckli 2 m n + () ? ------------------------- = n 015 {, } m 16 32 , {} , preliminary data sheet mas 3506d micronas 21 8e continued int selectfrequency ( double fstation) { double fq,fdiv; double fqmax = 0; int imax = 0; for ( int i=0;i<16;i++) { fdiv = 14725000/(2*(32+i)); fq = fstation/fdiv; fq = fabs(fq-floor(fq)-0.5)*fdiv; if (fq > fqmax) imax = i; } return imax; } modifications to this algorithm are applicable. it may be useful to finish this procedure if fqmax reaches a certain minimum value, or a preprocessed table for all possible am-carrier frequencies may be stored in rom for the controller. dccf continued dc/dc-converter voltage the output voltage is selected with bits 16...14 and 9. there is a threshold between the output voltage of the dc/dc converter and the internal voltage monitor. the pup signal becomes inactive when the output drops below the monitor voltage. setting bit [16:14] and [9] dc/dc-converter output voltage/v internal monitor voltage/v 1 11 0 1 10 0 1 01 0 1 00 0 0 11 0 0 10 0 0 01 0 0 00 0 1 11 1 1 10 1 1 01 1 1 00 1 0 11 1 0 10 1 0 01 1 0 00 1 3.57 3.46 3.35 3.25 3.14 3.04 2.94 2.83 2.73 2.63 2.52 2.42 2.32 2.22 2.12 2.02 3.38 3.27 3.16 3.06 2.95 2.85 2.75 2.64 2.54 2.44 2.33 2.23 2.13 2.03 1.93 1.82 table 3 ? 10: control registers, continued address (hex) r/w function default (hex) name mas 3506d preliminary data sheet 22 micronas c8 r pio-register the pio-register is used to monitor the actual status of the pio- pins for both, pio-output and pio-input lines. bit 0 of the pio reg- ister corresponds to pin pi0, bit 1 to pi1 etc. due to the latency of the mas 3506d only slow events (>1 ms) can be monitored. please also refer to section 4.6.3.2. bit [19] bc-frame-toggle output level toggles with each bc-frame, t frame = 432 ms bit [18] bcenable 0 use sid*, sii*, sic* 1 use sid, sii, sic bit [13] bc-frame-sync 0 cleared after sch-read operation 1 start of new frame bit [12] bc-sync 0 unsynchronized 1 synchronized to bc bit [8] decoding-error 0 no error 1 error or sync lost bit [4] mpeg-frame-sync 0 cleared after anciliary data were read 1 sync to a new mpeg-frame bit [3] aud-sw this bit may be used to monitor a signal from the headphone jack that indicates switching between headphone and loudspeaker mode. bit [2:0] these three free input lines return the state logic level of the respective pio- pins. they may be used as a port expansion of the controller. pio table 3 ? 10: control registers, continued address (hex) r/w function default (hex) name preliminary data sheet mas 3506d micronas 23 3.5. control and status memory the memory cells given in the following sections may be read (section 3.3.9.) or written (section 3.3.7.) in order to observe or control the operation of the mas 3506d. note! memory cells not given in the tables must not be written. table 3 ? 11: control and status memory cells address (hex) r/w function default name d1:7ee r main status indicator of the bc-decoder the status cell returns global status information about the world- space decoder. its value is also returned by the ?default read? command as described in section 3.3.10. bit [15:12] bri bit rate index 0 reserved 1...8 n*16 kbit/s bit [11:8] nsc zero-based number of available service components 0 1 sc available ... ... 7 8 scs available bit [7:4] reserved bit [3] mcrc mpeg crc error 0 no crc-error in the last bc-frame 1 crc-error occured in the last bc-frame bit [2] mfs mpeg frame sync indication 0 no mpeg synchronisation 1 mpeg synchronisation bit [1] bcs broadcast channel frame sync indication 0 no bc synchronisation 1 bc synchronisation while the signals mpeg-frame-sync and bc-frame-sync in the pio-register c8 hex rise with the beginning of each frame, the signals mfs and bfs are stable as long as a valid bitstream is received. bit [0] s synchronized state 0 not in synchronized state (e.g. no bitstream) 1 mas 3506d is synchronized and decoding status mas 3506d preliminary data sheet 24 micronas d1:7ef r/w service component selection (0..7) and decoding control bit [15] outputmute 0 normal operation 1 mute output bit [14] autoscan autoscan function 0 disable autoscan function 1 enable autoscan function, skip non-audio scs bit [13] bcchange broadcast channel change 0 cleared on sch-rescynchronization 1 clears all previous sch-information setting this bit clears all previous sch-information and thus pre- pares the mas 3506d for a bc-change. this ensured the availabil- ity of the correct sch-data for the new bc. bit [12] mpegresync 0 allows resynchronization only after sch-detection 1 mpeg-resynchronization enabled bit [11:3] reserved, set to 0 bit [2:0] sc zero-based number of audio service component to be decoded 0 decode sc 1 ... 7 decode sc 8 numsc d1:7f0 r/w counter for broadcast channel frames bit [15:0] bccount counter for the decoded broadcast channel frames the bcframecnt ist incremented by one for each successfully decoded bc-frame (432 ms) since reset. this address is writable, thus the controller may reset/preset the content at any time to an arbitrary value. bcframecnt d1:7f1 r/w counter for mpeg frames bit [15:0] mpegframecnt counter for the decoded mpeg-frames the mpegframecnt ist incremented by one for each successfully decoded mpeg-frame (24...72 ms) since reset. this address is writable for a reset/preset. mpeg- framecnt table 3 ? 11: control and status memory cells, continued address (hex) r/w function default name preliminary data sheet mas 3506d micronas 25 d1:7f3 r system error indication bit [10:0] errorcode last error of worldspace decoding 1xx hex buffer problem, causes a firmware reset: 100 hex errorinputtimeout: input time-out 101 hex errorservicepreamblewrong: service preamble wrong 102 hex errorbufferoverflow: input buffer overflow 103 hex errorbufferunderrun: buffer underflow 104 hex erroroutputtimeout: output time-out 105 hex errorbitrateintexchanged: bitrate index has changed 106 hex errornolayer3syncnextfram: no synchro- nization found in input bitstream 2xx hex bc-error, causes a bc-resynchronization: 100 hex errorsctodecodeoutofrange: sc to decode is not available 101 hex errorsctypewrong: sc has no audio 1ff hex errorstartbcsync: the controller has indicated a bc-change (signal bcchange) 3xx hex mpeg-error, causes an mpeg- resynchronization: 300 hex errorsctodecodeuserchange: a new sc was selected 301 hex error: 302 hex error: 303 hex error: sampling rate changed if an error occurs during decoding of the broadcast channel bit- stream a number describing the error will be copied into this mem- ory cell. the content always keeps a value corresponding to the last detected error. errorcode d1:7f4 r/w counter for all decoding errors bit [15:0] errorcnt counter for all decoding errors the errorcnt is incremented by one for each decoding error since reset. this address is writable for a reset/preset. this counter is valuable for long-time observations. for identification of the last error see d1:7f3 errorcnt table 3 ? 11: control and status memory cells, continued address (hex) r/w function default name mas 3506d preliminary data sheet 26 micronas d1:7f5 r bits 12..16 of mpeg-header the mpegstatus1 memory cell provides a direct copy of bits 16...12 of the acual mpeg-header. this cell will be updated imme- diatley after the mpeg-header has beed read from the bitstream. bit [12:8] copy of bits 16...12 of the mpeg-header bit [12:11] mpegid bits 13 and 12 of the mpeg-header 00 mpeg 2.5 01 reserved 10 mpeg 2 11 mpeg 1 bit [10:9] layer bits 11 and 10 of the mpeg-header 00 reserved 01 layer 1* 10 layer 2* 11 layer 3 bit [8] protection 0 crc-protected 1 no crc bit [7] reserved bit [6:2] private bits bit [1] crc error 0no error 1 a crc-error has occured bit [0] invalid frame 0 normal operation 1 an invalid frame has occured mpegstatus1 table 3 ? 11: control and status memory cells, continued address (hex) r/w function default name preliminary data sheet mas 3506d micronas 27 d1:7f6 r bit 32...17 of mpeg-header the mpegstatus2 memory cell provides a direct copy of bits 32...17 of the acual mpeg-header. this cell will be updated imme- diately after the mpeg-header has beed read from the bitstream. mpegstatus2 mpeg 1 layer 3 mpeg 2 layer 3 mpeg 2.5 layer 3 bit[15:12] datarate in kbit/s 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 free 32 40 48 56 64 80 96 112 128 160* 192* 224* 256* 320* reserved free 8 16 24 32 40 48 56 64 80 96 112 128 144* 160* reserved free 8 16 24 32 40 48 56 64 80 96 112 128 144* 160* reserved bit[11:10] sampling frequency/khz 00 01 10 11 44.1* 48 32 reserved 22.05* 24 16 reserved 11.025* 12 8 reserved bit[9] padding bit bit[8] private bit bit[7:6] mode 00 stereo 01 joint stereo 10 dual channel 11 reserved bit[5:4] joint stereo: mode extension intensity stereo ms_stereo 00 off off 01 on off 10 off on 11 on on bit[3] copyright 0 not protected 1protected bit[2] original/copy 0copy 1original table 3 ? 11: control and status memory cells, continued address (hex) r/w function default name mas 3506d preliminary data sheet 28 micronas 3.5.1. volume matrix the digital baseband volume matrix is used for control- ling the digital gain as shown in fig. 3 ? 2. table 3 ? 12 shows the proposed settings for the four volume matrix coefficients for stereo, left, and right mono. the gain factors are given in fixed point notation as desribed in section 3.3.1. fig. 3 ? 2: digital volume matrix d1:7f6 continued bit[1:0] emphasis 00 none 01 50/15 s 10 reserved 11 ccitt j.17 d1:7f7 r/w configures the serial audio output interface bit [19:0] outputconfig 0 generate 32-bit audio samples 16 generate 16-bit audio samples outputconfig d1:7f8 r/w left ? left gain bit [19:0] ll left left gain (please refer to sections 3.3.1. and 3.5.1.) 80000 ll d1:7f9 r/w left ? right gain bit [19:0] lr left right gain 00000 lr d1:7fa r/w right ? left gain bit [19:0] rl right left gain 00000 rl d1:7fb r/w right ? right gain bit [19:0] rr right right gain 80000 rr * modes marked with an asterisk are not used in the worldspace system. table 3 ? 11: control and status memory cells, continued address (hex) r/w function default name table 3 ? 12: settings for the digital volume matrix memory lo- cation (hex) d1: 7f8 d1: 7f9 d1: 7fa d1: 7fb name ll lr rl rr stereo (default) ? 1.0 0 0 ? 1.0 mono left ? 1.0 ? 1.0 0 0 mono right 00 ? 1.0 ? 1.0 ? 1 ? 1 ? 1 ? 1 ll lr rl rr + + left audio right audio preliminary data sheet mas 3506d micronas 29 table 3 ? 13: volume matrix conversion (db into hexadecimal) volume (in db) hexa decimal volume (in db) hexa decimal volume (in db) hexa decimal volume (in db) hexa decimal volume (in db) hexa decimal 0 80000 ? 20 f3333 ? 40 feb85 ? 60 ffdf4 ? 80 fffcc ? 18deb8 ? 21 f4979 ? 41 fedbf ? 61 ffe2d ? 81 fffd1 ? 2 9a537 ? 22 f5d52 ? 42 fefbb ? 62 ffe60 ? 82 fffd6 ? 3 a5621 ? 23 f6f03 ? 43 ff180 ? 63 ffe8d ? 83 fffdb ? 4af3cd ? 24 f7ec8 ? 44 ff314 ? 64 ffeb5 ? 84 fffdf ? 5 b8053 ? 25 f8cd5 ? 45 ff47c ? 65 ffed9 ? 85 fffe3 ? 6bfd92 ? 26 f995b ? 46 ff5bc ? 66 ffef9 ? 86 fffe6 ? 7 c6d31 ? 27 fa485 ? 47 ff6da ? 67 fff16 ? 87 fffe9 ? 8cd0ad ? 28 fae78 ? 48 ff7d9 ? 68 fff2f ? 88 fffeb ? 9 d2958 ? 29 fb756 ? 49 ff8bc ? 69 fff46 ? 89 fffed ? 10 d785e ? 30 fbf3d ? 50 ff986 ? 70 fff5a ? 90 fffef ? 11 dbecc ? 31 fc648 ? 51 ffa3a ? 71 fff6c ? 91 ffff1 ? 12 dfd91 ? 32 fcc8e ? 52 ffadb ? 72 fff7c ? 92 ffff3 ? 13 e3583 ? 33 fd227 ? 53 ffb6a ? 73 fff8b ? 93 ffff4 ? 14 e675f ? 34 fd723 ? 54 ffbea ? 74 fff97 ? 94 ffff6 ? 15 e93cf ? 35 fdb95 ? 55 ffc5c ? 75 fffa3 ? 95 ffff7 ? 16 ebb6a ? 36 fdf8b ? 56 ffcc1 ? 76 fffad ? 96 ffff8 ? 17 edeb6 ? 37 fe312 ? 57 ffd1b ? 77 fffb6 ? 97 ffff9 ? 18 efe2c ? 38 fe638 ? 58 ffd6c ? 78 fffbe ? 98 ffff9 ? 19 f1a36 ? 39 fe905 ? 59 ffdb4 ? 79 fffc5 ? 99 ffffa mas 3506d preliminary data sheet 30 micronas 4. specifications 4.1. outline dimensions fig. 4 ? 1: 44-pin plastic metric quad flat package (pmqfp44) weight approximately 0.4g dimensions in mm fig. 4 ? 2: 44-pin plastic leaded chip carrier package (plcc44) weight approximately 2.5 g dimensions in mm note : the plcc44-package has limited availability caution: start pin and orientation of pin numbering is different for plcc and pmqfp-housings. spgs706000-5(p44)/1e 34 44 1 11 12 22 23 33 0.1 0.8 0.8 13.2 0.2 13.2 0.2 0.17 0.06 2.15 0.2 2.0 0.1 0.34 0.05 10 0.1 10 0.1 10 x 0.8 = 8 0.1 10 x 0.8 = 8 0.1 15.7 0.3 10 x 1.27 = 12.7 0.1 1.2 x 45 140 39 29 28 18 17 7 6 1.6 0.1 6 8.6 6 2 2 x 45 1.1 1.27 1.27 spgs704000-1(p44/k)/1e 17.52 0.12 17.52 0.12 16.5 0.1 16.5 0.1 10 x 1.27 = 12.7 0.1 4.75 0.15 4.05 0.1 1.9 0.05 0.27 0.03 0.71 0.05 0.48 0.06 0.9 0.2 preliminary data sheet mas 3506d micronas 31 4.2. pin connections and short descriptions nc not connected, leave vacant x obligatory, pin must be connected as described in application informations lv if not used, leave vacant vdd connect to positive supply vss connect to ground pin no. pin name type connection short description pmqfp 44-pin plcc 44-pin (if not used) 1 6 te i vss test enable 25por i vdd reset , active low 34i2cc io x i 2 c clock line 43i2cd io x i 2 c data line 5 2 vdd supply x positive supply for digital parts 6 1 vss supply x gound supply for digital parts 7 44 dcen i vss start and enable dc/dc converter 843eod o lv pio end of dma, active low 942rtr o lv pio ready to read, active low 10 41 rtw o lv pio ready to write, active low 11 40 dcsg supply vss dc converter transistor ground 12 39 dcso o vss dc converter transistor open drain 13 38 vsens i vdd dc converter voltage sense 14 37 pr i vdd pio dma request or read/write 15 36 pcs i vdd pio chip select , active low 16 35 pi19 o lv bc-frame-toggle 17 34 pi18 i vss bcinenable 18 33 pi17 i vss pio data [17], reserved 19 32 sic*/pi16 i x pio data[16] (sic*) 20 31 sii*/pi15 i vss pio data[15] (sii*) 21 30 sid*/pi14 i x pio data [14] (sid*) 22 29 pi13 o lv bc-frame-sync 23 28 pi12 o lv bc-sync 24 27 sod/pi11 o lv serial output data 25 26 soi/pi10 o lv serial ouput frame identification 26 25 soc/pi9 o lv serial output clock 27 24 pi8 o lv decoding-error 28 23 xvdd supply x positive supply of output buffers mas 3506d preliminary data sheet 32 micronas 29 22 xvss supply x ground of output buffers 30 21 sid/pi7 i x serial input data 31 20 sii/pi6 i vss serial input frame identification 32 19 sic/pi5 i x serial input clock 33 18 pi4 o lv mpeg-frame sync 34 17 pi3 i vss aud-sw, information from head- phone jack 35 16 pi2 i vss reserved 36 15 pi1 i vss reserved 37 14 pi0 i vss reserved 38 13 clko o lv clock output (nominal 24.576 mhz) 39 12 pup o lv power up, i.e. status of voltage super- vision 40 11 wsen i x enable dsp and dc/dc converter 41 10 wrdy o lv if wsen=0: valid clock input at clki if wsen=1: clock synthesizer pll locked 42 9 avdd supply vdd supply for analog circuits 43 8 clki i x clock input 44 7 avss supply vss ground supply for analog circuits pin no. pin name type connection short description pmqfp 44-pin plcc 44-pin (if not used) preliminary data sheet mas 3506d micronas 33 4.3. pin descriptions 4.3.1. power supply pins connection of all power supply pins is mandatory for the function of the mas 3506d. vdd supply vss supply the vdd/vss pair is internally connected with all digi- tal modules of the mas 3506d. xvdd supply xvss supply the xvdd/xvss pins are the supply lines for the pin output buffers. avdd supply avss supply the avdd/avss pair is internally connected with the analog blocks of the mas 3506d, i.e. clock synthe- sizer and supply voltage supervision circuits. 4.3.2. dc/dc converter pins dcen dc/dc enable in the dcen input signal starts and enables the dc/dc converter operation. dcsg supply the dc converter signal ground pin is used as a basepoint for the internal switching transistor of the dc/dc converter. it must always be connected to ground. dcso out dcso is an open drain output and should be con- nected with external circuitry (inductor/diode) to start the dc/dc converter. when the dc/dc converter is not used, it has to be connected to vss. vsens in the vsens pin is the input for the dc/dc converter feedback loop. it must be connected directly with the schottky diode and the capacitor as shown in fig. 2 ? 5 on page 10. when the dc/dc converter is not used, it has to be connected to vdd. 4.3.3. control lines i2cc scl in/out i2cd sda in/out standard i 2 c control lines. normally there are pull-up resistors from each line to vdd. 4.3.4. parallel interface control lines pr in pcs in rtr out rtw out eod out pio handshake lines. their use depends on the actual firmware on the mas 3506d. usage of these lines in the standard worldspace configuration is not planned. 4.3.5. parallel interface data lines general purpose parallel io pins. the information of the input and output signals may also be read from register c8 hex (please refer to table 3 ? 10 in section section 3.4. on page 20). pi19 bc-frame-toggle out the bc-frame-toggle output toggles its state after each correctly decoded broadcast channel frame (432 ms). this pin can be used for monitor the proper function of the system. pi18 bcinenable in pi18 is used as input pin to sense the status of the bcinenable line at the worldspace connector. on low input level the alternative bc-input lines sic*, sii* and sid* are activated and sic, sii, sid are deacti- vated. pi17 reserved in/out pi16 sic* in pi15 sii* in pi14 sid* in the sic*, sid*, and sii* may be configured as alterna- tive serial input lines in order to support alternative serial digital sources. sid* (pi14) is used as broadcast channel data input from the broadcast channel i/o interface. mas 3506d preliminary data sheet 34 micronas pi13 bc-frame-sync out the bc-frame-sync is reset after por and set to ? 1 ? after each correctly decoded sch. it will only be cleared if the controller reads out sch information from the mas 3506d. pi12 bc-sync out the bc-sync is set, if the mas 3506d is in the state of proper decoding of the broadcast channel bit- stream. pi8 decoding-error out the decoding-error pin is activated, if during decoding of the broadcast channel, the mpeg frame an error occurs or if no input bitstream is applied. pi4 mpeg-frame-sync in the mpeg-frame-sync signal indicates that an mpeg header has been decoded properly and the internal mpeg decoder is in a synchronized state. the mpeg-frame-sync signal is inactive after power- on reset and will be activated when a valid mpeg layer 3 header has been recognized. the signal will be cleared if the ancillary data information is read out by the controller via i 2 c interface. pi3 aud-sw in the aud-sw input may sense the headphone jack and deposit its information in bit 3 of register c8 hex (please refer to table 3 ? 10 on page 20.) this way the controller can get the information weather a loud- speaker or a headphone should be supplied and can set the bas_invr bit in drd 3515a ? s register glb_config accordingly. pi2 reserved in pi1 reserved in pi0 reserved in 4.3.6. voltage supervision and other functions clki in clko out clki and clko are the input and output clock lines to be connected to the drd 3515a. clki expects 14.725 mhz, clko delivers 24.576 mhz synchronous to the audio data stream. pup power up out the pup output indicates that the power supply volt- age exceeds its minimal level (software adjustable). wsen dsp enable in wsen enables dsp and dc/dc-converter operation. it must also be set to activate the control interface e.g. to reprogram the dc/dc-converter. wrdy out wrdy has two functionalities depending on the state of the wsen signal. if wsen = 0, it indicates that a valid clock has been recognized at the clki clock input. if wsen = 1, the wrdy output will be set to ? 0 ? until the internal clock synthesizer has locked to the incom- ing audio data stream, and thus, the clko clock out- put signal is valid. 4.3.7. serial input interface sid in sii in sic in data, frame indication and clock line of the serial input interface. the sii line should be connected with vss in the standard worldspace mode. the sid and sic lines are used for the broadcast channel input. preliminary data sheet mas 3506d micronas 35 4.3.8. serial output interface sod out soi out soc out data, frame indication and clock line of the serial audio output interface (i 2 s). the soc line can be deactivated, if only the drd 3515a d/a converter is connected. the soi indicates, whether the left or the right audio sample is transmitted. in the default setting a left audio sample always corresponds to soi = low. 4.3.9. miscellaneous por in the power-on reset pin is used to reset the digital parts of the mas 3506d. te in the te pin is for production test only and must be con- nected with vss in all applications. 4.4. pin configuration fig. 4 ? 3: pmqfp44 package fig. 4 ? 4: plcc44 package 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 1234567891011 33 32 31 30 29 28 27 26 25 24 23 pi3 pi2 pi1 pi0 clko pup wsen wrdy avdd clki avss pi13 sid sii sic pi17 pi18 pi19 pcs pr vsens dcso sic sii sid xvss xvdd pi4 pi8 soc soi sod pi12 por i2cc i2cd vdd vss te dcen eod rtr rtw dcsg mas 3506d 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 avss clki avdd wrdy wsen pup clko pi0 pi1 pi2 pi3 dcso vsens pr pcs pi19 pi18 pi17 sic sii sid pi13 por i2cc i2cd vdd vss te dcen eod rtr rtw dcsg sic sii sid xvss xvdd pi4 pi8 soc soi sod pi12 mas 3506d mas 3506d preliminary data sheet 36 micronas 4.5. internal pin circuits fig. 4 ? 5: input pins pcs , pr fig. 4 ? 6: input pin te, dcen fig. 4 ? 7: input pins wsen, por fig. 4 ? 8: input pin clki fig. 4 ? 9: input/output pins pi0...pi4, pi8, soc, soi, sod, pi12.. . pi19 fig. 4 ? 10: input/output pins i2cc, i2cd fig. 4 ? 11: input/output pins dcso, dcsg fig. 4 ? 12: output pins wrdy, rtw , eod , rtr , clko, pup fig. 4 ? 13: input pin vsens fig. 4 ? 14: input/output pins sic, sii, sid ttlin xvdd p n xvss vdd n vss dcso dcsg vss xvdd xvss n p vsens vss xvdd p n xvss preliminary data sheet mas 3506d micronas 37 4.6. electrical characteristics 4.6.1. absolute maximum ratings stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.6.2. recommended operating conditions symbol parameter pin name min. max. unit t a ambient operating temperature ? 40 85 c t s storage temperature ? 40 125 c p max power dissipation vdd, xvdd, avdd 600 mw v sup supply voltage vdd, xvdd, avdd 5.5 v v idig input voltage, all digital inputs ? 0.3 v sup +0.3 v i idig input current, all digital inputs ? 20 +20 ma i out current, all digital output 0.5 a i outdc current dcso 1.5 a v ii2c input voltage, i 2 c-pins i2cc, i2cc ? 0.3 5.5 v symbol parameter pin name min. typ. max. unit t a ambient temperature range ? 40 85 c v sup supply voltage vdd, xvdd, avdd 2.7 3.0 3.6 v reference frequency generation clk f clock frequency clki 14.725 mhz clk i_v clock input voltage 0 v sup v clk amp clock amplitude 0.5 v pp mas 3506d preliminary data sheet 38 micronas levels i il27 input low voltage at v sup = 2.7 v ... 3.6 v por i2cc, i2cd, dcen, wsen 0.4 v i ih36 input high voltage at v sup = 2.7 v ... 3.6 v 1.8 v i ih33 input high voltage at v sup = 2.7 v ... 3.3 v 1.7 v i ih30 input high voltage at v sup = 2.7 v ... 3.0 v 1.6 v i ild input low voltage pi 1) , sii, sic, sid, pr, pcs, te, 0.4 v i ihd input high voltage v sup ? 0.5 v t rf rise/fall time of digital inputs pi, sii, sic, sid, pr, pcs, clki 10 ns d cycle duty cycle of digital clock inputs sic, clki 40 50 60 % dc-dc converter external circuitry c 1 blocking capacitor (< 100 m ? esr) 2) vsens, dcsg 330 f v f schottky diode forward voltage 3) dcso, vsens 0.35 v l inductance of ferrite ring core coil 4) dcso 22 h 1) i = 0 to 4, 8 , 12 to 19 2) sanyo oscon 6sa330m (distributed by endrich bauelemente, d-72202 nagold-lselshausen) 3) zetex zmcs1000 (distributed by zetex, d-81673 m nchen), standard schottky 1n5817 4) c8 r/4l, sds0604 (distributed by endrich bauelemente, see above) symbol parameter pin name min. typ. max. unit preliminary data sheet mas 3506d micronas 39 4.6.3. characteristics at t = t a , v sup = 2.7 to 3.6 v, typ. values at t a =27 c, v sup = 3.5 v, clk f = 14.725 mhz, duty cycle = 50% symbol parameter pin name min. typ. max. unit test conditions supply voltage i sup current consumption vdd, xvdd, avdd 32 ma 2.7 v, sampling frequency 32khz 17 ma 2.7 v, sampling frequency 24 khz 11 ma 2.7 v, sampling frequency 12 khz digital outputs and inputs v dol output low voltage soi 1) , soc 1) , sod 1) , eod, rtr , rtw , wrdy, pup, clko pi 0.3 v i load =6ma v dih output high voltage v sup ? 0.3 vi load =6ma z digi input impedance pi, sii, sic, sid, pr, pcs, clki 7pf i dleak digital input leakage current ? 11 a0v preliminary data sheet mas 3506d micronas 41 4.6.3.2. timing of pio-signals behavior of the frame signals the bc-frame-toggle toggles its level from ? 1 ? to ? 0 ? and vice-versa every 432 ms. the bc-frame- sync signal is set to ? 1 ? after the internal decoding process for the service control header has been fin- ished for one frame. the signal could be used as an interrupt input for the controller that triggers the read out of the service control header. as soon as the mas 3506d has recognized the corresponding read command for the sch, the bc-frame-sync is reset before sending the first data word. the time t read depends on the response time of the controller. this behavior reduces the possibility of not recognizing the bc-frame-sync active state, if no controller inter- rupt line is available for this purpose. a similar behavior is implemented for mpeg-frame- sync signal. however the frame period is restricted to the mpeg frame length, the reset is initiated by issuing a ? read ancillary mpeg data ? command. fig. 4 ? 16: schematic timing of bc-frame signals table 4 ? 1: pio characteristics symbol parameter pin name min. typ. max. unit test conditions t bctp bc-frame toggle time pi19 432 ms v h v l 432 ms bc-frame-toggle (pi 19) 432 ms v h v l bc-frame-sync (pi13) t read mas 3506d preliminary data sheet 42 micronas 4.6.3.3. i 2 s bus characteristics ? sdi at t = t a , v sup = 2.7 to 3.6 v, typ. values at t a =27 c, v sup =3.0v, clk f = 14.725 mhz, duty cycle = 50 % fig. 4 ? 17: serial input symbol parameter pin name min. typ. max. unit test conditions t siclk i 2 s clock input clock period sic 480 ns multimedia mode, mean data rate < 150 kbit/s t siids i 2 s data setuptime before falling edge of clock sic, sid 50 t siclk - 100 ns t siidh i 2 s data hold time sid 50 ns t bw burst wait time sic, sid 480 h l h l h l t siclk t siidh t siids sic (sii) sid preliminary data sheet mas 3506d micronas 43 4.6.3.4. i 2 s characteristics ? sdo at t = t a , v sup = 2.7 to 3.6 v, typ. values at t a =27 c, v sup = 3.0 v, clk f = 14.725 mhz, duty cycle = 50 % fig. 4 ? 18: serial output 4.6.3.5. firmware characteristics at t = t a , v sup = 2.7 to 3.6 v, typ. values at t a =27 c, v sup = 3.0 v, clk f = 14.725 mhz, duty cycle = 50 % symbol parameter pin name min. typ. max. unit test conditions t soclk i 2 s clock output period soc 325 ns 48 khz stereo 32 bit/sample t soiss i 2 s wordstrobe delay time after falling edge of clock soc, soi 0ns t soodc i 2 s data delay time after falling edge of clock soc, sod 0ns h l h l h l t soclk t soiss t soiss t soodc soc soi sod symbol parameter min. typ. max. unit test conditions synchronization times t bcsync synchronization on broadcast channel 216 432 ms t mpgsync synchronization on mpeg bit streams 12..36 72 ms f s = 32 khz, mpeg 2.5 time constants t bcloop buffer controlled loop time constant (see fig. 2 ? 2 on page 8) 5 8 10 s step response t anc validity of ancillary data after rising edge of mpeg-frame-sync signal 6ms t sch validity of sch-data after rising edge of bc-frame-sync signal 400 ms ranges pllrange tracking range of sampling clock recovery pll ? 200 200 ppm mas 3506d preliminary data sheet 44 micronas 4.6.4. dc/dc converter characteristics at t = t a , v sup = 3.0 v, clk f =14.725mhz, f sw = 230 khz, typ. values at t a =+27 c. unless otherwise noted: v out =3.0v, v in =1.2v symbol parameter pin name min. typ. max. unit test conditions v in1 minimum start-up input voltage 1) 0.9 1.1 v i load =0ma dccf = $08000 (reset) v in2 minimum operating input voltage 1) 0.6 0.9 v i load =55ma, dccf = $08000 (reset) 1.3 1.8 v i load =250ma, dccf = $08000 (reset) v out output voltage range bits 16..14, bit 9 of dccf register (hex): 1c000 18000 14000 10000 0c000 08000 04000 00000 1c200 18200 14200 10200 0c200 08200 04200 00200 vsens 3.567 3.460 3.354 3.248 3.144 3.039 2.935 2.831 2.729 2.625 2.524 2.422 2.321 2.219 2.118 2.017 v vin = 1.2 v iload = 50 ma v otol output voltage tolerance vsens ? 3.6 3.6 % i load =50ma t j =27 c v in =1.2v i load1 output current vsens 150 ma v in = 0.9...1,5 v i load2 250 ma v in = 1.8...3.0 v dv out /dv in / v out line regulation vsens 0.35 %/v i load =50ma dv out /dv in / v out line regulation vsens 0.7 %/v i load =250ma, v out =3.5v, v in =2.4v dv out /v out load regulation vsens ? 0.5 % i load = 50...150 ma dv out /v out load regulation vsens ? 0.5 % i load = 50...250 ma, v out =3.5v, v in =2.4v preliminary data sheet mas 3506d micronas 45 1) all measurements are made with a c8 r/4l 20 h, 25 m ? ferrite ring-core coil, zetex zlmcs1000 schottky diode, and sanyo/oscon 6sa330m 330 f, 25 m ? esr capacitors at input and output. h max maximum efficiency 90 % v in =3.0v, v out =3.5v i supply supply current vsens 1.1 5 ma v in =3.0v, i load =0, includ. switch current i l,max inductor current limit dcso, dcsg 1.0 1.4 a r on switch on-resistance dcso, dcsg 0.4 ? i leak switch leakage current dcso, dcsg 0.1 1 at j =27 c, converter = off; i load =0 a f sw switch frequency dcso, dcsg 156 230 460 khz depending on dccf t start start-up zime asserting to pup dcen , pup 8msv in =1.0v, i load =1ma, puplim = 010 (reset) f startup vsense dcso 250 khz vsens < 1.9 v symbol parameter pin name min. typ. max. unit test conditions mas 3506d preliminary data sheet 46 micronas 4.6.5. typical performance characteristics fig. 4 ? 19: efficiency vs. load current load current (a) 0 20 40 60 80 100 efficiency (%) efficiency vs. load current (vout=2.7v) load current (a) 0 20 40 60 80 100 efficiency (%) efficiency vs. load current (vout=3.5v) load current (a) 0 20 40 60 80 100 efficiency (%) efficiency vs. load current (vout=2.2v) load current (a) 0 20 40 60 80 100 efficiency (%) efficiency vs. load current (vout=3.0v) 10 10 10 10 1 -4 -3 -2 -1 10 10 10 10 1 -4 -3 -2 -1 10 10 10 10 1 -4 -3 -2 -1 10 10 10 10 1 -4 -3 -2 -1 vin: 2.4v 1.8v 1.5v 1.2v 0.9v 0.7v vin: 3.0v 2.4v 1.8v vin: 2.4v 1.8v 1.2v vin: 1.5v 1.2v 0.9v 0.7v 3.0 v 1.8 v vin 0.7 v 2.4 v vin 0.7 v 1.5 v vin 2.4 v 1.2 v vin preliminary data sheet mas 3506d micronas 47 fig. 4 ? 20: output voltage vs. input voltage fig. 4 ? 21: output voltage vs. load current 1.5 2 2.5 3 3.5 input voltage (v) 2.6 2.8 3 3.2 3.4 3.6 output voltage (v) output voltage vs. input voltage iload=250ma 0.9 1.4 1.9 2.4 2.9 input voltage (v) 2 2.2 2.4 2.6 2.8 3 3.2 output voltage (v) output voltage vs. input voltage iload=50ma 3.5 v 3.1 v 2.7 v 3.1 v 2.2 v 2.7 v 0 0.1 0.2 0.3 load current (a) 2.6 2.8 3 3.2 3.4 3.6 output voltage (v) output voltage vs. load current 0 0.02 0.04 0.06 0.08 load current (a) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 output voltage output voltage vs. load current vin=3v, 2.4v, 1.8v vin=2.4v vin=1.5v, 0.9v vin=1.5v, 0.9v vin vin vin mas 3506d preliminary data sheet 48 micronas fig. 4 ? 22: maximum load current vs. input voltage fig. 4 ? 23: no load supply current vs. input voltage 0 1 2 3 input voltage (v) 0 0.2 0.4 0.6 0.8 maximum load current (a) maximum load current vs. input voltage vout= 3.5v 3.1v 2.7v 2.2v 3.5v 2.2v v out 0 1 2 3 input voltage (v) 0 2.0 4.0 6.0 no load supply current vs. input voltage v out =3v preliminary data sheet mas 3506d micronas 49 fig. 4 ? 24: load transient-response fig. 4 ? 25: line transient-response fig. 4 ? 26: startup waveform 500.00 s/div v in = 1.2 v; v out =3v 1 load current 200.0 ma/div 2 output voltage 100.0 mv/div / ac-coupled 3 inductor current 500.0 ma/div 3v 0a 0a i load =100ma; v out =3v 1v in 2.000 v/div 2 output voltage 50.00 mv/div / ac-coupled 3 inductor current 200.0 ma/div 5.00 ms/div 3v 2v 200 ma v in =1v; i load =0ma 1 v (dcen) 2.000 v/div 2 v (pup) 2.000 v/div 3 inductor current 500.0 ma/div 4 output voltage 2.000 v/div 500 s/div 0a 3v 3v 3v mas 3506d preliminary data sheet 50 micronas preliminary data sheet mas 3506d micronas 51 all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. mas 3506d preliminary data sheet 52 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-433-1pd 5. data sheet history 1. preliminary data sheet: ? mas 3506d worldspace broadcast channel audio decoder, july 25, 2001, 6251-433-1pd. first release of the preliminary data sheet. |
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